1. Field of the Invention
This invention relates generally to a method of fabricating a microelectronic die, and more specifically to a method for increasing electron mobility values of channel regions of semiconductor transistors.
2. Discussion of Related Art
Transistors that make up integrated circuits of microelectronic dies are manufactured in and on silicon or other semiconductor substrates. Such a transistor has a channel region and source and drain regions on opposing sides of the channel region. The transistor further has a gate dielectric layer and a gate electrode which are formed on the channel region. A voltage that switches on the gate electrode can switch a current that flows between the source and drain regions through the channel region.
It has been recognized that a large tensile stress can increase both electron mobility of N-MOS devices and hole mobility of P-MOS devices. Several approaches to inducing strain in silicon have been proposed, including mechanical deformation of silicon wafers, local stressing of devices with thermal-expansion mismatched films, and the use of graded layer epitaxy of silicon germanium (SiGe) films on silicon followed by silicon epitaxy on the relaxed SiGe. The degree of stress that can be provided by these processes is usually relatively limited, which, when making a C-MOS wafer, necessitates that a tensile stress be provided for an N-MOS device and a compressive stress for a P-MOS device.